AI-Driven Chip Testing on the Cloud
Keywords:
Semiconductor testing, semiconductor diagnostics, data engineering, cloudscale development, cloud-scale data engineering .Abstract
The semiconductor testing process is a key bottleneck in the chip manufacturing flow. To address this inefficiency, data engineering pipelines have been built in the cloud that unify the ingest of test vectors and rich parametric telemetry for real-time testing and AI-powered diagnosis. New chips are tested using algorithms that can decide whether to release or scrap a chip based on the test results and preceding telemetry. Because clearance decisions are made during test, failed chips can quickly be relabeled or logged without being held in test. Data science pipelines examine failed chips and use the conclusions from these analysis to detect issues in other chips in near real-time. Such AI-powered diagnostics also have the potential to help prevent future recurrences. Acting on these insights can ultimately improve yield and shorten test time for future designs.
Data pipelines are about two orders of magnitude less expensive than the test process. They enable continuous decision-making for testing, clearance, and failure analysis without manual steps and facilitate timely action based on telemetry and failed part diagnostics. Making the testing process more efficient can represent significant cost savings for high-volume products. Ultimately, delivering better and cheaper parts to customers faster improves competitiveness and profitability.
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